1. Field of the Invention
Embodiments of the present invention generally relates to methods for high temperature etching of high-k materials, more specifically, for high temperature etching high-k materials during the fabrication of gate structures.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate pattern is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die. Typically, a gate structure comprises a gate electrode disposed over a gate dielectric layer. The gate structure is utilized to control a flow of charge carriers in a channel region formed between the drain and source regions beneath the gate dielectric layer.
High-k dielectric materials (e.g., materials having a dielectric constant greater than 4) have been widely applied as the gate dielectric layer in the gate structure applications. High-k gate dielectric materials provide a low equivalent oxide thickness (EOT) and reduced gate leakage. Although most high-k materials are relatively stable at ambient temperatures, these materials have proven to be difficult to etch during a gate structure manufacture sequence. Additionally, conventional etchants have low selectivity to etch high-k materials over other materials present in the gate structure, such as gate electrode and/or underlying materials, thereby leaving silicon recess, foot, or other associated defects on the interface of the high-k materials over other materials.
Therefore, there is a need in the art for improved methods for etching high-k materials during fabrication of a gate structure.